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  1. Esterel EDA

    ESL-to-RTL synthesis for control-intensive IP design and verification.
    RTL2
    VHDL1
    Verilog1
    code generation1
    SystemC1
    formal methods1
    correct by construction1
    ESL synthesis1
    automated implementation1
    Electronic System Level1
    unambiguous specifications1
    Esterel Studio0

    www.esterel-eda.com - 2009-02-09

code generator1 c++3 power estimation1 j2ee2 java4 power4 asp4 power grid analysis1 english4 .net3 esl2 asp.net3 efl2 post3 php5 database4 language3

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